2.1 Current Pipelined Systems in Microprocessors and Fast Real-Time Electronics
Pipelining is an implementation technique used to speed up CPUs or trigger systems in High Energy Physics (HEP), in which multiple instructions (or operations) are overlapped in execution. An instruction of a CPU (or trigger electronics in HEP) can be divided into small steps, each one taking a fraction of the time to complete the entire instruction. Each of these steps is called a pipe stage or pipe segment (see FIG. 1, where St—1=Stage 1). The stages are connected to one another to form a pipe.
The instruction (or datum in HEP) enters one end and exits from the other. At each step, all stages execute their fraction of the task, passing on the result to the next stage and receiving from the previous stage simultaneously. The example described herein refers to a speed of 40 MHz, but is not limited to that speed. Rather, the described approach applies to any speed which can be achieved with any technology.
Stage 1 either receives a new datum from the sensors every 25 ns and converts it from analog to digital in HEP, or fetches a new instruction in a CPU. The complete task (instruction in a CPU) is executed in the example of FIG. 1 in 5 steps of 25 ns each. In such a pipelined scheme, each stage has an allocated execution time that cannot exceed the time interval between two consecutive input data (or instruction in a CPU).
The pipelining technique has been used for many years in computer CPUs, and has subsequently been used also by the designers of the first-level triggers for HEP.